Thus far, a semiconductor device in which a plurality of semiconductor chips are stacked to form a three-dimensional configuration and thereby downsizing is achieved has been used. For example, in an imaging device, a light receiving element chip that is a semiconductor chip having a configuration in which pixels each including a light receiving element are arranged in a two-dimensional array configuration and a peripheral circuit chip formed of a peripheral circuit that drives the light receiving element chip are manufactured separately on the basis of the respective manufacturing processes. After that, a manufacturing method in which these chips are joined together and stacked and thereby the imaging device is configured is employed. In a case where such a manufacturing method is employed, it is desirable to enhance the joining strength at the joining surface in order to improve the reliability of the imaging device.
On the joining surface of these chips, pads electrically connected to a circuit in the semiconductor chip are arranged; and the transmission of electrical signals between the chips is enabled by these pads being joined together. These pads are configured with a metal such as copper (Cu), and therefore a relatively high joining strength can be obtained. On the other hand, an insulating layer for insulating the pads etc. is placed in regions other than the pads of the joining surface. The joining strength between these insulating layers is lower than the joining strength between the pads; hence, a system that activates the joining surface by plasma treatment to improve the joining strength is proposed (e.g., see Patent Literature 1.).